NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications

December 12, 2019 Tiera Oliver

SmartDV Technologies, a choice for Verification Intellectual Property (VIP), announced NSITEXE licensed its TileLink VIP to complete verification of its semiconductor IP adaptable to various applications using the RISC-V architecture.

SmartDV's VIP verifies the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based or alternative architecture system-on-chip (SoC) designs.

According to Hideki Sugimoto, chief technology officer (CTO) at NSITEXE, Choosing SmartDV's TileLink VIP was a smart decision for its power-efficient data flow processor (DFP) IP used in in-vehicle, industrial applications, and other market segments.

SmartDV will exhibit at the RISC-V Summit (Tuesday, December 10) from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m. at the San Jose Convention Center, San Jose, Calif. It will highlight the TileLink VIP and its Verilator VIP, and demonstration its Smart ViPDebug, a visual protocol debugger that reduces debug time. Attendees can schedule demos or meetings at demo@smart-dv.com.

For more information, please visit: www.Smart-DV.com

About the Author

Tiera Oliver, edtorial intern for Embedded Computing Design, is responsible for web content edits as well as newsletter updates. She also assists in news content as far as constructing and editing stories. Before interning for ECD, Tiera had recently graduated from Northern Arizona University where she received her B.A. in journalism and political science and worked as a news reporter for the university's student led newspaper, The Lumberjack.

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