SmartDV Technologies, a choice for Verification Intellectual Property (VIP), announced NSITEXE licensed its TileLink VIP to complete verification of its semiconductor IP adaptable to various applications using the RISC-V architecture.
SmartDV's VIP verifies the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based or alternative architecture system-on-chip (SoC) designs.
According to Hideki Sugimoto, chief technology officer (CTO) at NSITEXE, Choosing SmartDV's TileLink VIP was a smart decision for its power-efficient data flow processor (DFP) IP used in in-vehicle, industrial applications, and other market segments.
SmartDV will exhibit at the RISC-V Summit (Tuesday, December 10) from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m. at the San Jose Convention Center, San Jose, Calif. It will highlight the TileLink VIP and its Verilator VIP, and demonstration its Smart ViPDebug, a visual protocol debugger that reduces debug time. Attendees can schedule demos or meetings at firstname.lastname@example.org.
For more information, please visit: www.Smart-DV.com
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