Cobham Gaisler, a UK aerospace and defense supplier, announced at the RISC-V Summit in San Jose, California, that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx' Kintex UltraSCALE FPGAs.
The NOEL-V is dual-issue, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable stores and cache refill.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug and play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
The initial RISC-V product will be an RV64GC compliant processor Intellectual Property (IP) core, a 64-bit architecture, written in VHDL. The processor will be fully integrated with Cobham's GRLIB VHDL IP core library. GRLIB offers interfaces and functions such as high-speed serial interconnect, encryption, compression, etc., to which the RISC-V processor can interface. It will be complemented with the upgrade of the GRMON3 Software Debug Monitor to support the new ISA.
The processor is the first released model in Cobham Gaisler's RiSC-V line of processors that complement the LEON line of processors. Cobham also announced a new LEON5 processor core, further broadening its portfolio of SPARC processors.
For more information about Cobham Gaisler's NOEL-V processor, please visit: https://www.cobham.com/advanced-electronic-solutions.aspx#
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