Silexica announced the release of SLX FPGA 2020.2 which includes usability improvements for HLS users.
The new Vivado/Vitis HLS project importer enables engineers to import an existing Xilinx HLS project to evaluate and get started with SLX FPGA. According to the company, the update features further optimizations in the SLX FPGA analysis engine, combining both static and dynamic analysis, results 7x faster, and analysis time during parallelism detection.
An overview of how SLX FPGA addresses the needs of new and advanced HLS users is demonstrated in Silexica's latest blog article High-Level Synthesis: How to solve common challenges for new and experienced users. It shows how SLX FPGA enables new HLS users to be successful in their first design by providing an understanding of the multiple options to fix synthesizability issues and exploit parallelism.
SLX FPGA tackles the problems associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, application parallelism detection, and determination of which pragmas to insert and the pragma attributes to help engineers prepare and optimize their C/C++ application code for HLS.
New Usability Enhancements Include:
- New Vivado/Vitis project importer to get started easier with SLX FPGA;
- Faster analysis time to enable more design exploration;
- Alignment of compiler versions between Silexica and Xilinx for ideal compiles;
- Function Mapping Editor has been extended with additional interface types.
For more information, visit: www.silexica.com
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