OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation

December 12, 2019 Tiera Oliver

With the CORE-V Chassis project, OpenHW Group, a company that provides infrastructure for hosting open-source HW developments, aims to tape out a heterogeneous multi-core processor evaluation SoC, capable of running the Linux operating system during the 2nd half of 2020. The CORE-V Chassis will see a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core.

Based on the proven NXP iMX platform, the resulting CORE-V Chassis evaluation SoC will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP)DDR4, and multiple SDIO interfaces, along with a range of further peripheral blocks.

The 64-bit CV64A core in the CORE-V Chassis is based on the RV64GC RISC-V core IP, originally developed as part of the PULP Platform at the University of ETH Zurich. The CV64A core will be capable of clock frequencies of 1.5GHz and alongside the CV64A, is a highly capable CV32E coprocessor core based on the RV32IMFCXpulp RISC-V core IP, also from the University of ETH Zurich.

The CORE-V Chassis announcement is an open call for industry participation in this ambitious project.  OpenHW Group welcomes organizations that want to get involved and help shape the direction of the CORE-V Chassis initiative.

For more information please visit:

About the Author

Tiera Oliver, edtorial intern for Embedded Computing Design, is responsible for web content edits as well as newsletter updates. She also assists in news content as far as constructing and editing stories. Before interning for ECD, Tiera had recently graduated from Northern Arizona University where she received her B.A. in journalism and political science and worked as a news reporter for the university's student led newspaper, The Lumberjack.

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