Keysight Announces the First Complete Design and Test Solution for Next Generation DDR5 Memory

January 23, 2020 Tiera Oliver

Keysight Technologies, Inc. announces the first design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems.

Running at twice the data rate of DDR4 results in shrinking design margins. It becomes difficult to optimize the printed circuit board (PCB) to minimize the effects of jitter, reflection and crosstalk. Heavily distorted signals can be recovered with decision feedback equalization (DFE), a new addition for DDR5 DRAM that disrupts the traditional measurement and simulation approaches used for earlier generations of DDR.


Ultra-low noise UXR0204A Real-time Oscilloscope for Transmitter Test, debug and Receiver stressed-eye calibration

Keysight's design and test workflow solution enables hardware engineers to meet their time-to-market window and deliver an end-product with: 

  • New transmitter test methods to measure the signal eye diagram after equalization.
  • New loopback bit-error-rate (BER) receiver tests to validate device and system reliability.
  • Logic analysis to debug complex DDR5 traffic transactions to identify the source of system instability.

Completing the solution is PathWave ADS Memory Designer for DDR5, a simulation environment that addresses the current challenges faced by designers with the following key features:

  • Ability to predict performance, optimize a design and perform virtual transmitter compliance test, before realizing the first hardware prototype.   
  • Reduced simulation setup time from hours to minutes with new features such as DDR components, smart wires and an intelligent memory probe.
  • Increased simulation accuracy for DDR5 by representing receiver equalization with IBIS Algorithmic Modeling Interface (IBIS-AMI) models, enhanced specifically for the requirements of DDR.

Keysight's design and test workflow solution consists of the following product portfolio:

  • Modeling and simulation (W2225BP)
  • Probing and interposers
  • Transmitter test with oscilloscopes and compliance software (Infiniium UXR, N6475A)
  • Receiver test fixtures
  • Receiver test solution for loopback Bit Error Rate Testing (M8020A, M80885RCA)
  • Logic Analysis (U4164A, B4661A)
  • Power rail probes (N7024A)

Additional information on PathWave ADS Memory Designer is available at the following:

Keysight will unveil the DDR5 at DesignCon 2020 (Booth 725).

More information is available at


About the Author

Tiera Oliver, edtorial intern for Embedded Computing Design, is responsible for web content edits as well as newsletter updates. She also assists in news content as far as constructing and editing stories. Before interning for ECD, Tiera had recently graduated from Northern Arizona University where she received her B.A. in journalism and political science and worked as a news reporter for the university's student led newspaper, The Lumberjack.

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