Breker Verification Systems, the leading provider of Portable Stimulus Standard (PSS)-compliant software, today announced its PSS-based Test Suite Synthesis includes a set of new efficiency features including Intelligent Coverage Targeting, Pre-Solve/Pre-Compile Test Application and RapidFire™ Test Scheduling.
The combination of efficiency features bundled into Breker's Intelligent Regression Optimization Solution on average saves 75% or more in execution time. Some emulation runtimes improve by an order of magnitude with the tool.
"As SoC verification solutions evolve, significant inefficiencies emerge that impact performance and achievable coverage," observes Adnan Hamid, Breker's president and chief executive officer. "Test Suite Synthesis provides the opportunity to correct these. It leverages coverage specifics to drive test production, avoids emulation testbench compilation and random solving during execution, and batches test sets together while eliminating redundant startup procedures."
Breker's Intelligent Regression Optimization Solution
New capabilities offered by Breker's Test Suite Synthesis solutions are part of its PSS-compliant Trek5 product portfolio.
Intelligent Coverage Targeting
Using Test Suite Synthesis, verification engineers can target specific coverage requirements to generate tests. A Portable Stimulus design intent model is analyzed to produce a report that compares coverage options and the minimum test sets required to achieve these. The intent specification can be graphically manipulated to choose key path coverage scenarios across the entire graph with the tool providing feedback about length and number of tests required. As a result, test suite content can be optimized for required coverage in advance of engine execution, while redundant tests that do not contribute to the required coverage are eliminated.
Pre-Solve/Pre-Compile Test Application
With Breker's Test Suite Synthesis Solution, the random solving process is run prior to verification engine execution, based on the intent specification. For simulation, this saves time by eliminating some constrained random solving during execution. For emulation, this enables a unique randomized test capability since emulators typically do not include solver engines.
In addition, because test suite synthesis content is C code for processors and I/O transactions, they can be loaded into the design memory after the SystemVerilog design code has been compiled, eliminating testbench recompile requirements. This is helpful for simulation and critical for emulation because it eliminates a high proportion of expensive recompiles later in the verification process.
These capabilities improve emulation use models by transforming two of the most significant problems associated with hardware-based verification. They also eliminate a common UVM-to-SoC emulation barrier by providing a mechanism for test synthesis-generated randomized UVM sequences to be reused during emulation.
RapidFire Test Scheduling
Testbenches often contain groups of sequences with common startup procedures. Test Suite synthesis makes it possible to batch together test vectors with the same start-up sequences for the design. This allows the design to be reset and booted, and for other housekeeping routines common to the test vector set to be run once. Tests can then be executed in succession, saving redundant re-boots, and eliminating time-consuming tool-to-tool communication.
Pricing and Availability
The Intelligent Regression Optimization Solution is available now as part of the Breker Trek5 product suite.
Pricing is available upon request.
Breker at DVCon India
Breker will exhibit at DVCon India Wednesday and Thursday, September 25 and 26, at the Radisson Blu Bengaluru in Bangalore, India.
Dave Kelf, Breker's vice president and chief marketing officer, will present "Short Workshop: Leveraging Virtual Realization to Make Portable Stimulus UVM/SDV Scenarios Portable" at 4 p.m. Wednesday, September 25.