We will participate in the DVCon Conference and Exhibition, March 2-5 2020 at the Double Tree Hotel, San Jose, California. We'll be showcasing our latest verification solutions including the recently announced reference model with UVM encapsulation for RISC-V verification and a new collaboration with Mentor on the latest hardware Design Verification (DV) flow for RISC-V processor implementations.
As well as exhibiting on booth #1001 you can see us present a technical paper and participate in a panel discussion:
“Rolling the dice with random instructions is the safe bet on RISC-V verification” – by Simon Davidmann, CEO Imperas. Tuesday March 3, track session 3:00pm – 5:00pm
The traditional SoC verification approach has until now been based on the fundamental assumption of known good processor IP from the mainstream semiconductor IP providers. With Open ISAs such as RISC-V, developers can exploit a greater degree of implementation flexibility, but must also assume a greater role in the verification task. To complement the established technique, this paper illustrates the approach using an open-source random instruction generator for RISC-V with a cloud-based environment for capacity flexibility, to compare implementation RTL against a reference simulation model. This latest framework covers the needs of specialist core designers and all SoC adopters.
“New chip designs create tidal wave of change” – panelist Simon Davidmann, CEO Imperas. Wednesday March 4, 8:30am – 9:30am
DVCon attendees are invited to attend a Town Hall discussion on the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V.
For more information or to meet with someone from the team to discuss RISC-V reference models for processor verification and compliance, including draft specifications for Vectors and Bit Manipulation at DVCon, please get in touch here.