Visible Benefits - Aldec Makes Available a '4k Ultra HD Image Pass-through' Reference Design for Users of its Xilinx Zynq UltraScale+

October 16, 2018 Declaration Limited
Above, and being showcased at Arm TechCon 2018, is the demo unit for Aldec’s  4k Ultra HD image pass-through reference design, available for users the company’s TySOM™-3-ZU7EV embedded development kit.
Above, and being showcased at Arm TechCon 2018, is the demo unit for Aldec’s 4k Ultra HD image pass-through reference design, available for users the company’s TySOM-3-ZU7EV embedded development kit.

Aldec, Inc., an industry leader in electronic design verification, announces the immediate availability of a 4k Ultra HD image pass-through reference design for users of its TySOM-3-ZU7EV embedded development kit.

The TySOM-3-ZU7EV features a Xilinx Zynq UltraScale+ MPSoC device, which provides 64-bit processor (dual-core ARM Cortex) scalability and contains all the necessary connectivity and processing power to acquire, process and send high-resolution 4K (at 60fps) image data via the QSFP+ interconnect standard.

“Modern image broadcast technologies rely on real-time high-resolution image transmission, between an image producer and several image consumers,” comments Radek Nawrot, Director of Operations at Aldec. “To reduce bandwidth without sacrificing image quality, many emerging applications are calling for codec protocols such as QSFP+. Our reference design enables engineers to fast-track the implementation of 4k Ultra HD image transfer into their designs plus, of course, QSFP+ has applications outside of image transfer too.”

Aldec provides a HW/SW co-simulation solution for Zynq-based applications using Riviera-PRO, the company’s popular functional verification tool; when used in conjunction with open-source Quick Emulation (QEMU).

Nawrot continues: “We’re keen to support our customers as much as possible and we’re delighted to have received very positive feedback on our ever-expanding range of reference designs, which allow engineers to accelerate their design and verification activities.”

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