eSilicon Completes Tapeout of 7nm 400G Gearbox/Retimer Test ASIC

May 3, 2019 Brandon Lewis

SAN JOSE, CA. eSilicon has completed the tapeout of a 7 nm test ASIC that supports 400G gearbox and retimer functionality. The test ASIC includes x4 112 Gbps SerDes and x8 56 Gbps SerDes, which are integrated with media access control, forward error correction, and gearbox E-pak Ethernet IP from Precise-ITC. Technology in the chip will provide the foundation for developing 400G and 800G systems.

A gearbox converts multiple serial data streams at one rate to streams at another rate, while a retimer improves signal integrity by equalizing, retiming, and reconditioning received signals so that their range can be extended. eSilicon’s StarDesigner 7 nm flow was used in the design of the test ASIC to help meet stringent performance parameters, including long reach, low power, and low latency.

The test ASIC will be out of fabrication in September 2019, at which point eSilicon will release measurement and availability information.

The 7nm gearbox/retimer test ASIC will be out of fabrication in September, 2019. eSilicon will announce silicon measurement data and availability at that time.

For more information on eSilicon’s 7 nm IP, visit

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at

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