Andes certifies Imperas models, simulator as reference for Andes RISC-V Vectors Core

December 9, 2019 Perry Cohen

Imperas Software, a virtual platforms and software simulation company, announced a  collaboration with Andes Technology for the latest Andes Vectors Core NX27V. The collaboration addresses the requirement for advanced machine learning and artificial intelligence applications. Using Imperas models and tools allows system designers to evaluate advanced SoC architectural analysis using virtual platforms and full software application workloads.

The Vector extensions are designed to support complex arithmetic operations required for applications involving linear algebra, such as supercomputers, cryptography, AI, ML, and deep learning. A traditional, or scalar ISA, is based around operations on single data items, while a Vector processor operates over an array of data items which enables acceleration of key computational workloads.

Imperas will demonstrate solutions and tools for RISC-V including models and virtual platforms at the RISC V Summit in San Jose.

For more information, visit www.imperas.com/riscv.

About the Author

Perry Cohen

Perry Cohen, associate editor for Embedded Computing Design, is responsible for web content editing and creation in addition to podcast production. He also assists with the publication’s social media efforts which include strategic posting, follower engagement, and social media analysis. Before joining the ECD editorial team, Perry has been published on both local and national news platforms including KTAR.com (Phoenix), ArizonaSports.com (Phoenix), AZFamily.com, Cronkite News, and MLB/MiLB among others. Perry received a BA in Journalism from the Walter Cronkite School of Journalism and Mass Communications at Arizona State university. He can be reached by email at perry.cohen@opensysmedia.com Follow Perry’s work and ECD content on his twitter account @pcohen21

Follow on Twitter Follow on Linkedin More Content by Perry Cohen
Previous Article
Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors

Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices.

Next Article
SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit

VIP Ensures Thorough, Seamless Coverage-Driven Verification Flow Between Simulation, Emulation, Formal Veri...