This is part four of a series. Read part three here.
Protocols are ubiquitous in a large-scale design: supporting communications, graphics, memory, cache coherent interconnects, and so on and they are forever being updated to support the demand for more speed, higher bandwidth, lower power. So, you can be pretty sure that by the time you start your next project there will be new versions of at least some of the protocols in the design, for in the world of protocols standards bodies it is evolve, innovate or die.
For simulation, it is a relatively straightforward. Verification IP typically supports multiple simulators with the most common simulator methodologies of Verilog and UVM. You just need to make sure your provider stays up to speed with the latest versions.
In the emulation world, it is different. There are different types of “Verification IP” targeted for the different use-models: Simulation Acceleration, ICE and Virtual ICE. Simulation acceleration, for example, can give 1000x speedup over testbench based simulation. It “simply” requires UVM or SystemVerilog Verification IP with synthesizable transactors that replace simulation-based verification IP. It enables engineers to move a testbench, with the DUT running in a simulator, to run much faster with the DUT on an emulator. However, ICE is the more traditional use model of emulation and the most interesting use-case, and the point of this article is the shift from ICE to Virtual ICE.
ICE was the original method used to connect a design in the emulator to the outside world. It enabled external hardware to stream protocol-based traffic into the design. It used rate adaptors to take care of speed differences between the traffic generator and the emulator. An ICE environment was by necessity based in a lab located close to the engineers using it.
However, the ICE-age is rapidly melting as engineers realize the key benefits that virtual environments bring: accurate performance measurement, deterministic latency, and accurate power measurement. For storage and networking, the key metric is being able to accurately measure latency and performance, so it is essential to have pre-silicon performance measurements very close to the post-silicon performance that will be seen in the lab. Virtual enables this and by doing so allows pre-silicon performance tuning and trade-offs between hardware and software. This can be the difference between success and failure in our performance critical world. For improved debug Virtual ICE enables precisely repeatable behavior: with ICE it has been notoriously difficult to precisely repeat a sequence of behavior that uncovered a bug, making it very difficult to repeat a problem and find the cause. The future is clearly virtual!
Mentor took the leadership in Virtual ICE many years ago with the release of its VirtuaLAB components, a broad family of fully featured protocols. Mentor’s VirtuaLAB components behave like ICE but without the limitations of hardware-based solutions. They are flexible and reconfigurable on-the-fly, and with more verification features than their more primitive kin. VirtuaLAB models are in place for all of the key protocols including Ethernet, PCI Express, USB, NVMe, SATA, HDMI and so on and have been widely used in the successful tape out of hundreds of designs.
SDN switch designers switched to this technology three to four years ago leveraging the availability of VirtuaLAB Ethernet: it is clearly impractical to hook up 100+ Ethernet ports, each with its Ethernet cable, using ICE. Network switch designers use VirtuaLAB Ethernet to stream traffic to 150+ Ethernet ports over high-speed CoModel channels, controlling the configuration of the switch with VirtuaLAB PCIe running live software. More recently, SSD controller designers are making the same transition with Virtual NVMe, PCIe and SATA and the teams making that transition are getting a huge advantage over their competitors stuck in the ICE-age.
Another big advantage of VirtuaLAB components is that they can be remotely re-configured, thus making it easy to share emulation resources between design teams working on different projects anywhere in the world. Mentor has been perfecting this capability for several years now as part of its enterprise emulation applications.
Of course, key to an effective Virtual ICE solution is performance. For all its limitations, ICE is able to stream traffic at the same speeds to maximize emulator speed. With virtual you want to keep that same level of performance but be dependent on the connection speed and bandwidth between the host PCs controlling and generating traffic and the emulator. With many years of experience developing high-speed co-model channels, Mentor has tuned this performance to achieve equivalence with ICE speeds. Other solutions anecdotally experience a slowdown. This is not a software, fix it is a fundamental architectural feature of the emulator.
Mentor is clearly leading the way in the industry migration from ICE to Virtual ICE.
What Protocols We’re Watching at Mentor
We take our cues both from what customers ask for and from the protocol special interest groups. These days, they keep us busy with the latest versions of PCIe, Ethernet, NVMe, and so on to support leading edge designs in software-defined networks (SDN) and SSDs.
PCIe 4.0, having experienced several delays, is now available and the PCIe 5.0 specification is targeted for release in Q2, 2019. PCIe will also form the basis for other new protocols like Gen-Z, CCIX, and OpenCAPI.
- Ethernet is getting both higher speeds and acceptance in automotive applications. For the latter, significant new requirements are in place for safety, RFI, EMI, and latency.
- And SDN systems will gradually replace single-purpose routers and switches, especially in data centers, requiring them to handle a wide range of protocols implemented and configured by software.
Mentor has complete solutions for all mainstream (and also some niche) protocols that let you verify IP and SoC designs with transactors or via software. We keep a presence in critical standards organizations so that we can ensure the most effective emulation support for evolving and emerging protocols. And we have led the way with over five years of Virtual ICE implemented in the VirtuaLAB family, bringing the protocol expertise needed for us to support our customers as they differentiate their products.
Mentor’s Veloce Strato emulator family, combined with virtual protocol models and interconnected by CoModel channels, provides the most effective solution for proving that your design interacts flawlessly with any of the protocols it incorporates. With scalability to 15 billion gates on Veloce Strato, you can look forward to many years of worry-free verification.
Neill Mullinger, Product Marketing Manager, Mentor, a Siemens Business
Neill Mullinger is a senior product marketing manager in the EDA industry with more than 20 years of experience of verification technology and verification IP (VIP) for interface protocols. After building a strong base in verification over many years as an applications engineer, he is currently using his deep knowledge of protocol use in emulation-based transactors to accelerate the release and adoption of new technology.
Mentor, A Siemens Business