Once upon a time, hardware and software engineers mostly lived in their own worlds. The hardware team designed the chips, debugged the first samples back from the foundry, and tossed them “over the wall” for the software team to test their code. As virtual platforms and other executable models became more common, the software team could get started before the chips were fabricated, and sometimes fairly early in the development process. There was more schedule overlap but still limited interaction between the teams.
The rise of system-on-chip (SoC) designs with embedded processors has brought a dramatic change in the way that hardware and software are developed. Since the processors control most of the SoC’s functionality, verification teams routinely simulate code running on these processors. Since RTL simulation is slow, the industry has seen a huge increase in the use of emulation and FPGA prototyping. Modern verification technologies, including the portable stimulus standard under development within Accellera, span multiple verification platforms.
Writing the code to run on embedded processors during verification is a key challenge. Quite often, embedded programmers join the hardware verification team to perform this task. One result of this organizational change has been earlier and greater interaction between the embedded software and hardware teams. The more general-purposes CPUs, offload engines, and other programmable cores that appear in the SoC, the more involvement by the embedded software team. They’re working side by side with design and verification engineers developing the SoC.
Embedded programmers remain closely involved beyond simulation; their tests on hardware platforms or actual silicon typically look rather different from simulation testbench code. The tests should be tuned to take advantage of each platform’s unique characteristics. For example, slow simulation favors short tests with constant checking of results while silicon works best with long tests and accumulated results. This tuning prevents download time for code or upload time for results from compromising the processors’ blinding speed.
Of course, ultimately the SoC must run the production software so there’s usually an effort to run this software as soon as possible. This may happen as early as virtual platforms and RTL simulation, and is common during emulation or FPGA prototyping. Portable stimulus techniques can generate embedded test cases for all verification and validation platforms, and are effective at finding hardware bugs before production software is run. It is easier to debug a failing test case than a hang in the operating system or application.
One measure of how closely hardware and software development are intertwined is the technical program for the third annual Design and Verification (DVCon) India show in Bangalore September 15-16. There are a number of sessions and talks that show how the traditionally separate domains are growing ever closer, including:
- Hardware/Software/Embedded Co-design for Early Development
- Hybrid Solution Combining Hardware Emulation and Virtual Prototyping for Early Software Development
- UVM-based SoC Verification Methodology to enable vertical/horizontal reuse across RTL integration hierarchies and workstation RTL simulations to emulation to post silicon
- Development of a Virtual Platform for early software enablement for NFV
- How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges
- Using Portable Stimulus for SoC Verification as Applied on Mobile, Networking, and Server Designs
While hardware and software development are likely to remain separate disciplines for many engineers, their teams are working more closely than ever. The demand for earlier production software verification, software-driven tests for SoC verification and validation, and portability across verification platforms are all driving evolution in the same direction. There will likely be a corresponding evolution for existing standards such as UVM and in the development of new standards, including portable stimulus.
Thomas L. Anderson is Co-Chair of the DVCon India Promotions Committee and Secretary of the Accellera Portable Stimulus Working Group (PSWG). He serves as vice president of marketing at Breker Verification Systems, a SoC verification company. He has more than a dozen years of experience in EDA verification applications and marketing. Anderson holds a BS degree in Computer Systems Engineering from the University of Massachusetts at Amherst and a MS degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).