In our Deep Green Editor's Choice section, we look at technology helping design green into today's new products.
This month’s news features a variety of ideas that randomly crossed my desk: a new DSP core for Systems-on-Chip (SoCs) that carefully manages power, a Power Line Communications (PLC) chip with Orthogonal Frequency Division Multiple Access (OFDMA) for high-noise smart grid environments, and a unique approach to an Electronic Design Automation (EDA) design flow that has a big payoff for SoC designers.
DSP performance with power savings
DSPs are critical to portable multimedia devices, but achieving high performance while keeping power managed and in bounds for the expectations of battery-powered operation are two things that haven’t gone together very well. Finding a way to deliver more DSP performance while keeping power in check creates an interesting breakthrough.
CEVA’s latest DSP core, the CEVA-X1643, offers 1 GHz processing speed with an integrated Power Scaling Unit (PSU) that handles advanced power management for both dynamic and leakage power. The PSU controls the multiple clock sources and power domains within the core, plus multiple operational modes from full on to debug bypass to memory retention to complete power shutoff. The AXI bus interfaces also offer low-power features, like shutting off when no traffic is running.
Power line communications goes OFDMA
Defense and broadband communications networks have used frequency agile radios for years to avoid jamming and provide robust communications. One constant characteristic of the smart grid is noise – big loads quickly switching and often making a lot of electrical noise on a power line. Combine those two ideas in this latest innovation.
Semitech’s SM2200 PLC chip brings an OFDMA transceiver to the task of managing data over power lines, such as those used for the smart grid. It adapts to the noise environment, choosing the most effective frequency to operate, and uses a multi-access scheme to help simultaneously communicate with multiple nodes. The SM2200 can be easily combined with a microcontroller to build data links.
EDA design flow powers down SoCs
One of the biggest topics at this year’s Design Automation Conference was low-power design flows. It’s not news that as speeds get faster and geometries get smaller, dynamic and leakage power in an SoC become bigger problems. Optimizing power in a design flow can be a time-consuming, hand-crafted effort that can introduce more errors and slow down the whole process.
Calypto Design Systems, Virage Logic, and the Semiconductor Technology Academic Research Center (STARC) came together to take on a major component of SoC power: on-chip memory. Calypto’s PowerPro MG makes memory gating logic that works hand in hand with memory modes like light sleep, deep sleep, and shutdown in Virage Logics’s SiWare memory compilers. The memory compiler automatically generates a PowerPro MG model, which STARC has implemented in a seamless, low-power EDA design flow. The collaborating companies claim 50 percent dynamic power reduction and 40 percent leakage power reduction with the approach, which is outstanding news for SoC designers.