RISC-V processor trace IP released by UltraSoC

January 25, 2018 ECD Staff

UltraSoC has announced general availability of its RISC-V processor trace solution. Processor trace functionality allows the behavior of a program to be viewed in detail, instruction-by-instruction, and is a key requirement for system developers. The UltraSoC RISC-V trace encoder supports both 32 and 64-bit RISC-V designs, and the IP block integrates smoothly with the rest of the UltraSoC portfolio. 

The trace capability is backed by major RISC-V processor vendors, including Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore, and tools vendors.

“RISC-V is redefining the SoC value proposition: a key part of that is building a much more open and robust ecosystem than developers have been used to," says Rick O’Connor, executive director of the non-profit RISC-V Foundation. "On the technical level, full availability of processor trace is a key part of that development ecosystem. Within the RISC-V Foundation, we’re working to standardize the interfaces to RISC-V cores that provide processor trace; we’re delighted to see UltraSoC supporting that effort, while also delivering commercially.”

UltraSoC will be at Embedded Word 2018 (Nürnburg, Germany, 27th February – 1 March), exhibiting within the RISC-V booth in hall 3A, booth 3A-419. UltraSoC CEO Rupert Baines has been selected to present a paper at 10am, on 27th February alongside Russ Klein of Mentor Graphics, entitled ‘RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity’. The session will form part of the RISC-V Class, a full day of RISC-V focused discussions and presentations. For more details on the event and to arrange a meeting, visit the event page on the UltraSoC website.

eletter-01-29-2018
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