Imperas releases RISC-V Processor Developer Suite

November 29, 2017 ECD Staff

Oxford, UK. Imperas Software Ltd. has released a Developer Suite for the RISC-V architecture, including models and tools for validating and verifying the functionality of a RISC-V processor. The RISC-V Processor Developer Suite also enables estimation of a processor’s timing and power consumption.

Specifically, the RISC-V Processor Developer Suite includes:

  • Reference models for design verification
  • Fast processor models, an instruction set simulator (ISS), and extensible virtual platforms
  • Processor model instruction code coverage and profiling
  • A standard software toolchain including compiler, linker, debugger, and Eclipse integration
  • Timing performance and power estimation tools
  • Multiple test suites for measuring processor quality
  • Infrastructure for evaluating RISC-V conformance

All RISC-V features are implemented in supported models, and extendable with user-defined instructions, registers, and accelerators. Imperas currently supports RV64/32 IMAFDC (GC) models, Andes V5 RISC-V based cores, and Extendable Platform Kits (EPKs) of Microsemi RISC-V-based devices running FreeRTOS (available on the Open Virtual Platforms (OVP) website).

For more information, visit

Previous Article
Silicon Labs biosensors add ECG measurement for advanced heart rate monitoring in wearables

The Si117x sensor modules combine ultra-low power and high sensitivity, making them ideal for wrist-based, ...

Next Article
GE Power adds dual redundancy to RX3i CPE400 industrial controllers
GE Power adds dual redundancy to RX3i CPE400 industrial controllers

The redundancy features are easy to configure, and powered by the PACSystems’ High Availability solution ov...