Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface

October 23, 2018 Agnisys
Agnisys at DVCon Europe
Agnisys at DVCon Europe

MUNICH, GERMANY – October 16, 2018 – Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), will present the latest release of IDesignSpec at DVCon Europe in Munich, Germany on October 24-25, 2018.

“The latest release of IDesignSpec includes several new features to address emerging challenges associated with HSI particularly for large SoC designs,” said Anupam Bakshi, CEO. “Our customers across the globe predominantly develop the newest and greatest SoCs in the market and their requirements continue to push our product capabilities towards unexplored territories – helping us innovate further.”

IDesignSpec 6.16 includes the following new useful capabilities, and supports new standards:

 

– Ability to compare two register specification files in various formats; proven useful for projects with distributed teams.

 

– The latest SystemRDL 2.0 standard release from Accellera is now supported as both input and output files.

– Supports YAML, a popular human-readable data serialization language commonly used for configuration files available as plain text input and output.

– Vertical Reuse, enables lower level specification and corresponding design and verification to be used at higher levels, thus saving resources.

 

– Complete testbench creation from specification.

 

– Generates multiple hierarchical output for technical documentation; proven useful for large SoC datasheet generation.

 

About IDesignSpec

IDesignSpec is an award-winning solution that helps IP/SoC design architects and engineers create executable specification for registers and automatically generate output for SW/HW teams. The specifications can be written in Word, Excel or LibreOffice with the editor Plugin or text-based industry standard formats including SystemRDL 2.0, RALF or IP-XACT. IDesignSpec captures simple as well as special registers, signals, interrupts, and then generates synthesizable RTL code and interfaces to AMBA AXI, AXI4Lite, AHB, APB, AHB3Lite and other standard buses.

 

About Agnisys

Agnisys Inc. is the leading supplier of Electronic Design Automation (EDA) software for solving complex design and verification problems for system development. Its products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) enabling faster design, verification, firmware, and validation. Based on patented technology and intuitive user interfaces, Agnisys products increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Boston, Massachusetts with R&D centers in the United States and India. www.agnisys.com

 

Media Contact

 

Contact: Louie de Luna

 

Phone: +1 855-VERIFYY

 

Email: marcom@agnisys.com

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