Squeezing the last penny of efficiency from embedded designs

November 1, 2010 OpenSystems Media

4Not every processor is built on cutting-edge processes - many processors are being designed around mature nodes to reduce risk and cost. As with any embedded System-on-Chip, the challenge is to become more power-efficient. Physical IP can help extend battery life by reducing dynamic and leakage power.

The embedded microcontroller and mixed-signal System-on-Chip (SoC) markets have shown strong growth while manufacturing on mainstream technology process nodes. At almost $30 billion, the mixed-signal market constitutes about 10 percent of the $300 billion semiconductor industry, and this growth will continue with the advent of new consumer applications. For example, touch-screen technology and cell phones existed independently for many years. The emergence of better human user interfaces in the form of smartphones has established a market that did not exist three years ago.

Mixed-signal circuitry is what enables our analog “real” world to interact with its electronic digital counterparts. As embedded applications continue to reach higher volumes and more mobile implementations, designers are confronting the issues of lowering costs and reducing power.

A challenge in embedded and mixed-signal designs is the cost-sensitive nature of high-volume design. The lower the product price, the greater the number of potential applications that can incorporate that technology. One semiconductor cost-reduction approach is fabrication in small process geometries. But in the mixed-signal market, there are several reasons why developers stay on mainstream nodes:

  • Analog components do not scale as well as digital components on a semiconductor process. As a result, the density benefits of scaling are much less than those obtained by digital components.
  • Most mixed-signal devices do not have the high-speed requirement of digital devices. Many mixed-signal devices operate at speeds of less than 100 MHz, which eliminates the need to quickly move to the next leading process node.
  • Older process technologies are stable with well-understood analog characteristics. The low risk and low cost make manufacturing at the older technology nodes more compelling.

Embedded SoC designers must look for innovative solutions to reduce die size while remaining on mainstream process technologies.

Another challenge for embedded designers is power reduction. At 250 nm, foundries are not investing in the process innovations necessary to reduce dynamic and leakage power. Some applications need additional power optimization to increase battery life to 2-5 days, as is the case with smartphones. Some medical applications such as pacemakers need low-power solutions to enable batteries to last 5-10 or more years. Nano- or pico-amp usage can minimize extensive surgeries and thereby increase patient quality of life.

Whether an application is on an extreme of the battery life continuum or somewhere in the middle, the one constant is that users need more functionality on a single charge. The embedded designer’s challenge is to increase functionality while staying at a low risk – on a mature process node – and decrease area and power for added feature and battery life differentiation.

Feature innovation with embedded processors

Mixed-signal SoCs either incorporate a low-power microcontroller or work with a stand-alone microcontroller to execute commands from the user and address interrupts and provide readings of incoming data. ARM offers a family of modern 32-bit processors, the Cortex-M series, specifically designed for low-power microcontrollers.

To address the requirement for additional features, these processors offer more performance at a given footprint via performance efficiency – the ability to complete tasks faster and therefore reduce activity periods. The performance advantage stems from Cortex-M performing single-cycle 32-bit arithmetic and logic operations (including single-cycle 32-bit multiplication) and performing 8-, 16-, or 32-bit data transfers with indexed addressing in a single instruction. This dramatically reduces the processor clock frequency required and increases the performance from a single instruction. Furthermore, it reduces the memory required for program storage and the power needed to fetch programs from memory.

The reduced clock frequencies mean lower-noise and higher-precision analog, boosting the device’s analog sensor capability. RF applications also benefit from the reduction of electromagnetic interference. This efficiency increases performance and provides low-noise, high-precision analog operation ideally suited for mixed-signal applications.

Reducing manufacturing risk and silicon area

Increased functionality from an efficient processor design is a great start, but embedded designers also need to decrease SoC area and retain a low-cost, low-risk process node. To meet this need, the increasing trend is to migrate to the mainstream 180 nm node. Some of the most aggressive designs are even targeting the 110 nm technology node to shrink die size. Several factors are enabling this trend:

  • Twelve-year-old 180 nm technology is stable enough that there is little to no risk in migrating from 250 nm technology to 180 nm.
  • The availability of value-adding nonvolatile memory components such as flash and one-time programmable memory is not offered at the 250 nm node.
  • Emerging niche process technologies like 180 Ultra-Low Leakage (ULL), 180 Bipolar CMOS DMOS (BCD), and 110 ULL are perfectly suited for the embedded market with their low dynamic and leakage power profiles.

Optimized Physical IP for reduced area and power

Area reduction leads directly to decreased die cost, and combined with lower power, can enable less expensive SoC packaging and cut overall system costs. Furthermore, lower dynamic and leakage power extends battery life. ARM enables reduced die size and power with Physical IP platforms implemented on ULL processes.

The ULL Physical IP platform comprises a range of logic products: a nine-track SC9 High-Density (HD) standard cell library, a tapless seven-track SC7 Ultra-High-Density (UHD) standard cell library, and a seven-track SC7 UHD Power Management Kit (PMK). The platform contains a full range of memory compilers including HD SRAMs, register files, and ROMs. The SC7 UHD library typically delivers up to 30 percent area savings compared to the SC9 HD library (see Figure 1).

Figure 1: The SC7 Ultra-High-Density library saves up to 30 percent of the area on the ARM Cortex-M0.

The SC7 UHD library can be paired with the complementary SC7 UHD PMK, which can, for a small logic area increase, result in significant leakage savings. For example, when implementing the Cortex-M0, the leakage using SC7 is 12x lower compared to that of the SC9. When implementing with the SC7 UHD library and SC7 UHD PMK, the Cortex-M0 has up to 50x reduction in leakage (see Figure 2).

Figure 2: Implemented with the SC7 Physical IP, the ARM Cortex-M has up to 50x reduction in sleep mode leakage.

The future of embedded and mixed-signal design

The embedded and mixed-signal markets will continue to grow with added innovations to increase features and differentiation while reducing costs. Efficient embedded processors and Physical IP will aid in the growth of these markets by providing unparalleled design and efficiency in tomorrow’s embedded device solutions.

ARM 32-bit processors bring added functionality and performance efficiency. Physical IP implemented on smaller, yet still low-risk process nodes will keep manufacturing costs low and reduce die size. Optimized solutions such as ARM’s Physical IP bring dramatic area and leakage savings for lower total system costs and extended battery life.

Figure 3

Kimkinyona Fox is a senior platform marketing manager at ARM, Inc. Her experience includes senior-level marketing and engineering positions at Rambus, Cypress, PLX Technology, and C-Cube Microsystems. Kimkinyona has authored multiple articles on high-speed interfaces and system design. She earned her BSEE from California Polytechnic State University, San Luis Obispo.

Raviraj Mahatme is a platform marketing manager with the Physical IP Division at ARM. He started his career with ARM as a circuit design engineer and has worked in multiple ARM offices around the world. He holds an MSCE from North Carolina State University, Raleigh.

ARM kimkinyona.fox@arm.com ravi.mahatme@arm.com www.arm.com

Kimkinyona Fox (ARM) and Raviraj Mahatme (ARM)
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