Verification IP: A Vital Component of Chip Design Verification

December 12, 2019 Bipul Talukdar, director of applications engineering, SmartDV’s

To many chip design verification engineers, VIP could easily stand for Very Important Possession and not Verification Intellectual Property (VIP).

VIP is considered a valuable component of a verification methodology as it describes libraries of reusable verification components and pre-defined functional blocks instrumental in validating the correctness of complex interfaces and protocols found in system-on-chip (SoC) designs. Covering the alphabet of MIPI, SerDes, automotive, memory models, networking, storage and video, they remove the need for experts in multiple protocols because they verify the design against the details of the protocol specification. Along the way, they improve debug, quality and coverage closure, accelerate project delivery, increase return on investment and reduce the risk of silicon respin.

A testbench for a complex SoC requires a variety of VIP blocks to verify system-level functionality and validate target performance by generating application-specific traffic and checkers. Blocks are inserted into the testbench for a design to check the operation of protocols and interfaces, both discretely and in combination. They enable verification engineers to inspect basic features, such as system start-up or more detailed exploration. This is increasingly important because of growing design complexity. They generate tests that stimulate and verify different interfaces and standard bus protocols, such as transactions/sequences, drivers and configuration components. A test plan for a specific interface and test suites connects to a design under test/verification (DUT) inside the testbench to simulate or emulate an IP or an SoC design. The result is an infrastructure for industry-standard interface and interconnect protocol support and a known reference to compare with the DUT.

While VIP is a proven and trusted verification commodity, it is not a verification methodology, unlike the universal verification methodology (UVM), an Accellera interoperability standard for building testbenches, or the Open Verification Methodology (OVM), a methodology and block library. They create an infrastructure to support industry-standard interfaces hardware verification languages (HVLs), SystemVerilog and SystemC and methodologies, UVM and OVM. VIP comes as industry-standard compliant, plug-and-play modules with a specific purpose: To verify system-level functionality and validate target performance while supporting all popular verification methodology platforms.

Verification engineers point to the need for thorough code coverage and functional coverage within a well-integrated flow. VIP supports a seamless coverage-driven verification flow with no coverage gaps between simulation, emulation or formal verification. It is usable at multiple stages in a design flow and by multiple suppliers to a design project.

VIP blocks for emulation and FFGA prototyping, for example, come as synthesizable register transfer level (RTL) code. Full API compatibility moves designs from simulation to emulation. These VIP blocks include built-in intelligent debuggers, offer fast compile and system-level simulation run times and fast firmware/software development. The infrastructure framework or testbench comes with stimulus generators, monitors, scoreboards/checkers and functional coverage models.

Within a simulation platform, VIP should not be tied to a specific simulator. Within an emulation platform, VIP should not be tied to an emulator. Similarly, VIP should not be tied to a specific formal

engine. For an ideal design, VIP needs to be platform agnostic and, even within the platform, verification engine agnostic for verification engineers to move from platform to platform seamlessly without any overhead in the process.

Whether it’s Very Important Possession or Verification Intellectual Property, verification groups use these blocks as part of their verification strategies and consider VIP to be a vital piece of the chip design verification flow.

 

About Bipul Talukdar

Bipul Talukdar is SmartDV’s director of Applications Engineering, North America. He is an expert in hardware functional verification with a specialty in Verification IP development, formal property verification and hardware emulation. Talukdar’s recent experience is in formal verification of RISC-V based cores and subsystems and coverage-based closure. He holds a Bachelor of Science degree in Engineering, Electronics and Telecommunication from the National Institute of Technology, Silchar in India.

Previous Article
NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications

Smart TileLink VIP to be Used to Ensure Complete Verification of High-Efficiency, High-Quality Semiconducto...

Next Article
Toshiba Using Cypress Semper Fail-Safe Storage with Next-Generation Automotive Advanced Driver Assistance Systems
Toshiba Using Cypress Semper Fail-Safe Storage with Next-Generation Automotive Advanced Driver Assistance Systems

Cypress Semiconductor announced Cypress’ Semper NOR Flash has been selected by Toshiba Electronic Devices &...