eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects

October 7, 2019 eSilicon

eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today its 7nm high-bandwidth interconnect (HBI™)+ physical interface (PHY) IP is available to be licensed for inclusion in customer designs. This special-purpose hard IP block delivers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications including system-on-chip (SoC) to chiplets and SoC partitioning for complex subsystems. Silicon interposer and silicon bridge technologies are supported.

eSilicon's HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 24 channels per PHY with one redundant lane per channel to improve production yields. The part also supports built-in self-test (BIST), internal loopback and external PHY-to-PHY link tests. Standards supported include IEEE 1149.1 (JTAG) and 1149.6 (AC JTAG) boundary scan.

"eSilicon has a rich history of developing high-performance, high-bandwidth interconnect IP, from long-reach SerDes to die-to-die interconnect," said Hugh Durdan, vice president, strategy and products at eSilicon. "This new HBI+ PHY will help to enable a growing chiplet ecosystem that is supported by many new and innovative technologies."

The prior version of this PHY (HBI, 2.5 Gbps per pin) was used successfully on a customer ASIC at 14nm. eSilicon is currently in design with a major customer ASIC in 7nm using the HBI+ PHY.

To learn more about eSilicon's 7nm and 5nm HBI+ PHY capabilities, you can visit its HBI web page or contact your eSilicon sales representative directly or via sales@esilicon.com.

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