Xilinx Adaptive Compute Acceleration Platform (ACAP) moves beyond FPGA

March 19, 2018 Brandon Lewis

SAN JOSE, CA. Xilinx has launched a new programmable chip architecture called the adaptive compute acceleration platform (ACAP). ACAP is a heterogeneous, reprogrammable multicore compute architecture that can be modified dynamically in milliseconds during operation to meet changing workload requirements. Xilinx claims that the 7 nm TSMC ACAP chips, the first of which are codenamed “Everest,” offer performance-per-watt characteristics “unmatched” by CPUs and GPUs.

ACAP is based on a new generation of FPGA fabric that includes hardware-programmable DSP blocks, a multicore system on chip (SoC), one or more hardware and software-programmable compute engines, and distributed memory connected in a network-on-chip (NoC) design (Figure 1). The integrated solutions are also equipped with programmable I/O functionality, which addresses memory controllers, SerDes, RF-ADCs/DACs, high-bandwidth memory (HBM), and so on. ACAP platforms can be programmed using C/C++, OpenCL, and Python, or programmed at the RTL level with FPGA tools.

Figure 1. Xilinx ACAP chips is based on a suite of hardware and software-reprogrammable engines, highly integrated programmable I/O, and IP subsystems connected via a network-on-chip (NoC) architecture.

The ACAP architecture targets unstructured Internet of Things (IoT) big data and artificial intelligence (AI) workloads such as AI inference, machine vision, data compression, network acceleration, computational storage, and video transcoding. According to Xilinx, the Everest platform is projected to deliver a 20x performance increase in deep neural network (DNN) processing over current-generation 16 nm Virtex VU9P FPGAs, and 4x 5G communications bandwidth.

The integrated compute platforms are scheduled to tape out later this year.

“While FPGA and Zynq SoC technologies are still core to our business, Xilinx is not just an FPGA company anymore,” says Victor Peng, President and CEO of Xilinx. “That is our heritage, but we have been building upon that foundation for years now: integrating full SoCs onto our programmable dies, developing 3D ICs, building out software development frameworks and creating partner ecosystems to deliver products that are completely unique to the industry,” says Peng. “We are taking this innovation to the next level with the invention of the ACAP, where we will deliver even more value to the data center and our core markets now, and into the future.”

More information is available at xilinx.com.


About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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