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Defining a New High-Speed, Multi-Protocol SerDes Architecture for Advanced Nodes

November 21, 2017

Designing a high-speed, high-performance serializer/deserializer (SerDes) for advanced process nodes can be challenging on many levels.

The speed (16Gbps) stresses the capabilities of even the most modern process with limited gain available and without area-intensive peaking inductors. The high channel loss (-30dB) requires a decision feedback equalization (DFE) architecture, and the low-power constraints preclude the use of speculative designs.

With multiple protocols and different processes in play, it’s difficult to optimize for a single set of requirements; this situation instead calls for more general solutions. For example, consider the emergence of FinFET processes. The FinFET process presents characteristics that are very different from those of prior semiconductor devices, such as high Rout (low gds), low static current densities, and very restrictive device sizing.

In response to these criteria, this paper defines a new high-speed, multi-protocol SerDes architecture that is ideal for meeting the challenges of advanced-node designs.

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