MathWorks, Microsemi collaborate on integrated FPGA-in-the-loop design workflow

April 19, 2018 Brandon Lewis

ALISO VIEJO, CA. MathWorks and Microsemi have announced an FPGA-in-the-loop verification workflow for PolarFire and SmartFusion2 FPGA development boards. The integrated workflow includes MathWorks’ HDL Coder and HDL Verifier, which allow engineers to automatically generate test benches for VHDL and Verilog to rapidly prototype and verify their designs.

As part of the collaboration, developers are able to leverage MATLAB and Simulink alongside Microsemi’s Libero SoC Design Suite. The integration allows bugs to be identified earlier in the design cycle.

“With the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware,” says Shakeel Peera, vice president FPGA marketing for Microsemi. “This integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero SoC Design Suite.”


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Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at

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