Imperas to Demonstrate Solutions for RISC-V Processor Verification and Extensions at Embedded World, Nuremberg 2020

February 24, 2020 Imperas

We'll be discussing all the latest demonstrations and virtual platform technology for RISC-V based designs, including verification and custom instruction as well as support for the latest RISC-V specifications for Vectors and Bit Manipulation.

In addition to exhibiting on the booth, we will also present two technical papers:

Wednesday 26 February, track session #4.3.1 @15:00
Discussing the virtual platform methodology employed by SAFEPOWER. Unique tools developed to provide observability into the hypervisor-based system are described, as well as the methods for providing timing and power estimation with sufficient accuracy.

For more information or to meet with us to discuss how to verify the RISC-V cores in your next design at Embedded World please get in touch here

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