GOWIN Adopts HyperBus Interface for Internal PSRAM, External HyperRAM

May 3, 2019 Brandon Lewis

SAN JOSE, CA and GUANGZHOU, CHINA. GOWIN Semiconductor Corporation now supports the HyperBus interface specification in their FPGA and programmable SoC solutions. HyperBus provides efficient use of package pins for high-speed interfacing with low pin count external memories, as well as internal PSRAM on GOWIN programmable devices. This helps reduce power, cost, and PCB footprint compared to legacy memory interface technologies.

The HyperBus interface consumes only 11 pins. Additional memories can be multiplexed with an additional chip select. Using GOWIN’s HyperBus Memory Interface IP core, processors can directly access up to 64 Mb of PSRAM over configurable 8-16-bit DDR bus widths, while external HyperRAM and HyperFLASH memories can also be connected.

GOWIN HyperBus Memory Interface, PSRAM, and Flash PSRAM devices are in production now. For more information visit www.gowinsemi.com/en/support/ip_detail/15.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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