Embedded Insiders Open Up on RISC-V Summit, MIPI Debug & Trace Specs

December 19, 2019 Brandon Lewis

The Insiders attended the second annual RISC-V Summit in San Jose earlier this month, and brought back some significant opinions about the show, the technology, and the direction of the RISC-V Foundation.

  • Is SiFive too powerful? 
  • Where are all the big semis? 
  • How does open hardware relate to Amazon, Apple, Google, and other tech giants building their own chips? And what does that mean for other chipmakers?

This episode also includes an interview with Enrico Carrieri, Chair of the MIPI Debug Working Group and Principal Engineer of Debug Architecture at Intel. Enrico puts his MIPI Alliance hat on to discuss the public availability of nine debug and trace specifications, which can be accessed directly from mipi.org. He also explains the importance of ecosystem enablement in the “necessary evil” world of debugging, and how new standards and tools can bring costs to a minimum.

Finally, a new segment with Jean Labrosse, Architect of the µC/OS RTOS, identifies “Things That Annoy a Veteran Software Engineer.” This week, he sounds off on following organizational coding standards.

Tune in.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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