Partial Reconfiguration (PR) allows FPGAs to dynamically change modules without disrupting other parts of the design. This is a feature that FPGA vendors are building into their newer generations of FPGAs, allowing for increased flexibility and functionality in digital systems. Users can partition the FPGA fabric into reconfigurable regions which are then reprogrammed using partial configuration files. PR proves beneficial in systems that communicate through PCIe™, which allows a user to dynamically reload a subset of the FPGA image without losing PCIe communication. It also provides a critical method of Intellectual Property (IP) protection as it removes the need to store sensitive data in nonvolatile memory on the FPGA carrier.
In the new Xilinx® RFSoC technology, PCIe PR through the Programmable Logic (PL) requires special considerations throughout the design process. This paper discusses the use cases of partial reconfiguration as well as considerations when designing partial reconfiguration firmware using the Xilinx Vivado design tool targeting the RFSoC.