X-FAB, Efabless Release First Silicon of “Raven” RISC-V SoC

June 13, 2019 Brandon Lewis

X-FAB and Efabless Corporation have announced first-silicon availability of Raven, an open-source SoC reference design based on the PicoRV32 RISC-V core. A mixed-signal SoC, nearly 75 percent of Raven’s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz.

Raven was created using an open-source design flow in less than three months. The chip is being manufactured on X-FAB’s automotive-grade 180 nm, 6-metal process, and supports a variety of optional features. These include:

  • Low-power option
  • On-chip isolation for high voltages
  • High-temperature flash memory

The semiconductor design is fully functional. The license-free reference design is available on the Efabless marketplace. The company is also engaged with initial customers on derivative designs.

Further technical details on the Raven chip can be found on Github.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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