IAR Systems, a supplier of software tools and services for embedded development, released a new version of the toolchain IAR Embedded Workbench for RISC-V. Version 1.20 adds support for the base instruction set RV32E, and the standard extension for Atomic operations.

Through optimization technology, IAR Embedded Workbench helps developers ensure the application fits the required needs and optimize the utilization of on-board memory. Version 1.20 of adds support for the base instruction set RV32E that targets smaller embedded devices with the register set reduced to half of what is available in RV32I. The standard extension for Atomic operations adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.

RISC-V is a free, and open instruction set architecture (ISA) is based on established Reduced Instruction Set Computing (RISC) principles.

IAR Systems is exhibiting at the RISC-V Summit Dec. 10-11, in San José, California. It will be demoing IAR Embedded Workbench for RISC-V.

For more information, visit www.iar.com/riscv.