Codasip and Metrics Design Automation jointly announced the integration of the Metrics SystemVerilog RTL Simulation Platform within Codasip's Pro SweRV Core Support Package. This integration provides a way for ASIC designers to verify modifications and enhancements they make to the SweRV embedded processor IP.

One benefit of the open source RISC-V ISA is that it allows users to customize their processor IP for optimal implementation in domain-specific applications. With this benefit however comes the responsibility to verify any changes made to the processor IP for functional accuracy. Codasip and Metrics have teamed together to address this requirement by making RTL verification available in the Cloud directly from the Codasip SweRV Core Support Package. SweRV and the Support Package users therefore do not have to install and license any EDA software, do not have to make any expensive purchases of RTL simulation software, and have all the SweRV and verification IP required all preloaded in a Cloud cluster for immediate use.

According to the companies, the Metric Cloud Simulator is a fully compliant SystemVerilog simulator and is the only RTL simulator available with a SaaS business model, users just pay for use as a service. The implementation of Metrics simulator in the Cloud provides scalability so regression tests can run in parallel to complete in hours, not days.

The SweRV Core Support Package with Metrics Cloud Simulation integration is available now.

For more information, visit: www.codasip.com/