CHIPS Alliance announced new enhancements to the SweRV Core EH2 and SweRV Core EL2, both of which were developed for the open-source community by Western Digital.
The CHIPS Alliance has been working to validate the cores since their release earlier this year.
According to the organization, the SweRV Core EH2, the world's first dual-threaded, commercial, embedded RISC-V core. Further, the SweRV Core EL2 ultra-low-power RISC-V core optimized for applications such as state-machine sequencers and waveform generators.
“Our work to help bring the newly enhanced SweRV Core EL2 and EH2 to the open hardware community demonstrates key progress towards our goal of accelerating RISC-V innovation,” said chairman of the CHIP Alliance Dr. Zvonimir Bandić, in a press release. “We’ve already seen significant industry interest in the SweRV Core EH1 and are pleased to offer two compelling additional options to engineers designing IoT, consumer, mobile and other embedded applications.”
The Alliance is hosting an online event to discuss the SweRV Core EH2 and EL2, May 20 at 5:30 p.m. PT.
To register for the CHIPS Alliance virtual event on May 20, please visit: https://zoom.us/webinar/register/WN_fbjiN5uvSuGbGdWUGlI65g.
To learn more about the SweRV Cores, please visit: https://github.com/chipsalliance/Cores-SweRV.
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