CEA-Leti Builds Fully Integrated, Bio-Inspired Neural Network

December 16, 2019 Perry Cohen

Leti, a technology research institute of CEA Tech, has fabricated a fully integrated bio-inspired neural network, combining resistive-RAM-based synapses and analog spiking neurons. Resistive-RAM (RRAM) is a type of non-volatile random-access computer memory that works by changing the resistance across a dielectric solid-state material.

Spiking neural networks are composed of bio-inspired neurons. They communicate by emitting spikes, or discrete events that take place at a point in time, rather than continuous values. These networks promise to further reduce required computational power because they use less complex computing operations, e.g. additions instead of multiplications. They also inherently exploit sparsity of input events, since they are intrinsically event-based.

The research work presented at IEDM 2019 measured a 5x reduction in energy use compared to an equivalent chip using formal coding. The neural network implementation is made such that synapses are placed close to neurons, which enables direct synaptic current integration.

About the Author

Perry Cohen

Perry Cohen, associate editor for Embedded Computing Design, is responsible for web content editing and creation in addition to podcast production. He also assists with the publication’s social media efforts which include strategic posting, follower engagement, and social media analysis. Before joining the ECD editorial team, Perry has been published on both local and national news platforms including KTAR.com (Phoenix), ArizonaSports.com (Phoenix), AZFamily.com, Cronkite News, and MLB/MiLB among others. Perry received a BA in Journalism from the Walter Cronkite School of Journalism and Mass Communications at Arizona State university. He can be reached by email at perry.cohen@opensysmedia.com. Follow Perry’s work and ECD content on his twitter account @pcohen21.

Follow on Twitter Follow on Linkedin More Content by Perry Cohen
Previous Article
OpenHW Group Announces CORE-V Chassis SoC Project
OpenHW Group Announces CORE-V Chassis SoC Project

The OpenHW Group aims to tape out a heterogeneous multi-core processor evaluation SoC capable of running th...

Next Article
Peering Through the Fog at SPS

Edge Computing and smart devices are an important part of Industry 4.0, and that reality was reinforced at ...