Oxford, United Kingdom, Sept. 20, 2017 — Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their Fast Processor Model and virtual platform support for the Synopsys DesignWare® ARC® EM processor family, available now, along with simulators, debuggers and other software test and analysis tools.
ARCv2 EM processors are optimized for use in embedded and deeply embedded applications where high performance with minimum power consumption is essential. The cores, based on the ARCv2 instruction set architecture (ISA), offer outstanding performance density, and are ideal for embedded applications in consumer, IoT, networking, automotive and other power- and cost-sensitive applications.
“Building on our partnership with Synopsys for ARC IP, Imperas is pleased to deliver our next-generation models, virtual platforms and software development solutions for the popular ARC EM cores, to help accelerate their adoption.” said Simon Davidmann, president and CEO of Imperas.
The comprehensive Imperas virtual platform environment for embedded software development, debug and verification for DesignWare ARCv2 EM cores includes Fast Processor Models and Extendable Platform Kits™ (EPKs™), with high-performance simulation, software debug, verification, analysis, and profiling (VAP) tools, and OS booting on the virtual platforms.
• EPKs are virtual platforms (simulation models) of the target devices, including processor and peripheral models sufficient to boot an operating system. EPK platforms are open source, so users can easily extend and customize the functionality, add new models, and modify existing models.
• Fast Processor Models work with Imperas and OVP simulators, delivering exceptional performance of hundreds of millions of instructions per second.
• Advanced Imperas software development solutions for multicore software development, verification, analysis and debug support the ARCv2 EM models. Solutions span analytical tools for hardware-dependent software development, with OS- and CPU-aware debug, tracing, profiling, code coverage, memory analysis, and innovative 3-dimensional (temporal, spatial and abstraction) debug capabilities.
The models of the ARCv2 EM processors, together with other OVP models, the OVP APIs and the OVPsim simulator, enable the building and customization of virtual platforms for custom SoC subsystems, full SoCs, and larger systems. These virtual platforms enable pre-silicon software development, accelerating software schedules, and more comprehensive testing, resulting in higher quality software.
Imperas will be attending the ARC Processor Summit 2017 on Tuesday, September 26th, at the Santa Clara Marriott in Santa Clara, CA. Please contact Imperas to set a meeting at firstname.lastname@example.org.
The addition of these ARC models expands existing Imperas and Open Virtual Platforms (OVP) platform support to over 170 processor models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn and twitter @ImperasSoftware.
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