SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India

September 16, 2019 SmartDV

WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, formal models and post-silicon validation platforms, Design IP and rapid customized VIP and Design IP development.

WHAT: Will demonstrate TileLink VIP used to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs at DVCon India. Another demonstration will showcase Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.

WHEN: Wednesday and Thursday, September 25 and 26. Attendees can schedule demonstrations through: demo@smart-dv.com

WHERE: Radisson Blu Bengaluru in Bangalore, India.

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