The company is due to present a paper outlining the technology at the International Electron Devices Meeting (IEDM) that takes place December 1 to 5 in San Francisco, California.
While this is an academic presentation and does not guarantee a commercial offering will follow, it seems likely that Intel will follow through, not least because TSMC is reported to be due to offer embedded MRAM at 22nm FinFET this year.
Flash memory, which was the embedded NVM of choice up until about 40nm process nodes, has difficulties scaling below 28nm. For this reason foundries Globalfoundries and Samsung have both offered embedded MRAM options in their fully-depleted silicon-on-insulator (FDSOI) processes (see Globalfoundries offers embedded MRAM on 22nm FDSOI and FDSOI to get embedded MRAM, flash options at 28nm).
However, integration with FinFET processes has been slower to appear. Back in 2017, Jack Sun, TSMC's CTO, was reported as saying that TSMC plans to enter so-called "risk production" of embedded MRAM in chips in 2018 using a 22nm manufacturing process. He was also reported as saying TSMC would offer embedded ReRAM in chips in 2019 (see Report: TSMC to offer embedded ReRAM in 2019).
At IEDM Intel researchers are expected to describe the successful integration of embedded MRAM into the company's 22nm FinFET CMOS technology on full 300mm wafers. The magnetic tunnel junction-based memory cells are built from dual MgO magnetic tunnel junctions (MTJs) separated by a CoFeB-based layer in a 1 transistor-1 resistor (1T-1R) configuration in the interconnect stack.
Intel has manufactured a 7.2Mbit array with reported data retention figures in excess of 10 years and write endurance of greater than 10^6 cycles.
The electron micrograph shows a cross-section of the MTJ array embedded between metal 2 and metal 4 in Intel's 22nm FinFET logic process.
Paper 18.1 is entitled 'MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology,' and is authored by O. Golonzka et al.