UltraSoC announced the release of the USB 2.0 IP, a solution designed to enable SoC and system development teams to access powerful system-level analytics, optimization and debug capabilities at speeds of 10Gbps. These features are obtainable even in a closed chassis.
USB 2.0 IP is structured around a patented hardware-based bare-metal technology. This technology doesn’t require software running to establish communication. Engineers can gather system performance data with access from cycle zero when 2.0 is combined with USB 3.1 from Synopsys.
Per the company, debug and analytics interface is subject to two vital design requirements. First, the interface itself must be robust in the event of system failure. If the system software fails to boot at start-up or crashes irretrievably during operation, it must still be possible to access the internal analytics, diagnostic and debug capabilities.
Further, CPU tracing capabilities and monitors can generate the data sets needed to be moved quickly off chip for analysis. The company says the combination of technology from UltraSoC and Synopsys satisfies both requirements.
For more information, visit www.ultrasoc.com.
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