Silicon Labs’ 5G-Ready Jitter Attenuators Future Proofed for 112G Serdes

June 20, 2019 Brandon Lewis

Silicon Labs has expanded its line of Si539x jitter attenuators with a fully integrated reference, allowing the devices to address reference clock requirements of 100G to 800G network designs. The 100 Hz to 1028 MHz Si539x devices support up to 12 different clock outputs, and are capable of meeting the jitter requirements of emerging 112G SerDes slated for deployment in emerging 5G network infrastructure applications.

The Si539x jitter attenuators are expected to be used with Ethernet switch ASICs, SoCs, FPGAs, and PHYs to help simplify circuit board design and layout. The integrated crystal reference provides high immunity to acoustic emissions, while also reducing PCB area requirements by more than 35 percent versus discrete timing solutions.

The Si539x jitter attenuators are available now, and can be evaluated on development boards priced at $299. Development is supported by Silicon Labs’ ClockBuilder Pro software.

More information can be found at www.silabs.com/timing.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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