Agnisys will present its SoC design and intellectual property (IP) solutions at the RISC-V Summit in San Jose, Dec. 10-12. The company will focus on showcasing how IDesignSpec along, with ARV and ISequenceSpec, enable software, hardware, verification, and validation engineers to accelerate their IP/SoC development cycle and mitigate the risk for first pass silicon.
They will showcase a flow using Agnisys software tools, wherein hardware and software teams can collaborate efficiently to easily create RISC-V based IPs/SoCs targeting both ASICs and FPGAs. Using IDesignSpec along with ARV, they will demonstrate how design teams can automatically generate the RTL from a golden register specification along with C-headers, UVM verification environment and virtual prototyping models for a variety of platforms and bus fabrics such as TileLink, AMBA® AXI, AMBA® AHB, AMBA® APB, Avalon® and custom.
The RISC-V summit in San Jose brings together RISC-V technology users, developers, and industry experts for three days of networking, sharing best practices on critical design and verification issues, discovering new techniques for designing advanced silicon, SoCs, and systems based on the RISC-V processor.
For more information, visit https://www.agnisys.com/events/risc-v-summit-2019/
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