Microchip’s PolarFire SoC FPGA Icicle Kit is an evaluation platform for the company’s mid-range PolarFire SoC FPGA family, a portfolio of RISC-V-based devices that contain secure hardware features, are capable of running off-the-shelf Linux and/or real-time operating systems (RTOS), and consume up to 60 percent less power than competing FPGA solutions, according to the company.

The SoC FPGA onboard the PolarFire SoC FPGA Icicle Kit, the MPFS250T-FCVG484EES, contains 254k logic elements with a four-input lookup table (LUT) and D-type flip-flop, 784 18x18 multiply accumulate (MACC) blocks, a five-core RISC-V CPU subsystem from SiFive, and 2 MB of L2 cache memory with support for deterministic modes (Figure 1). Data can also be stored off-chip in either a 2 GB LPDDR4, 1 Gb SPI flash, or 8 GB eMMC flash (muxed with an SD card slot) onboard the PolarFire SoC FPGA Icicle.

The RISC-V processor complex includes a 64-bit RISC-V monitor core with secure boot functionality alongside four 64-bit RISC-V application cores that connect to a coherency switch and then onto the memory subsystem. The coherent switch connects to a memory-protected and QoS-enabled AMBA switch over the AXI interface, and then on to the PolarFire FPGA fabric.

In terms of signals on the Icicle board itself, users will find a variety of interfaces and expansion ports for easy system integration and rapid prototyping, including:

• 4x 12.7 Gbps SERDES transceivers
• 2x PCIe Gen2 root port
• Dual Gigabit Ethernet (Microchip VSC8662XIC Ethernet PHYs and RJ45 connectors)
• Micro USB 2.0 Hi-Speed OTG4 x UART (Microchip USB3340 USB 2.0 Transceivers)
• 2x CAN
• 2x SPI
• 2x I²C
• mikroBUS socket
• Raspberry Pi-compatible 40-pin header

The I²C interface connects to a Microchip PAC1934T-I/JQ PMIC that performs FPGA and DDR power rail sensing. Meanwhile, an onboard JTAG connector and FlashPro6 programmer (onboard for production kits, external for prototyping kits) provide developers with direct debug access and an onramp to 52 test points.

GPIOs connect to User and Power LEDs, as well as a set of four pushbuttons.

The PolarFire SoC FPGA Icicle Kit in Action

The PolarFire SoC FPGA Icicle Kit’s biggest draw for most end users is support for both off-the-shelf Linux and bare metal/RTOS-based firmware. The SoC FPGA’s SiFive RISC-V CPU cores can be configured as either application processors or real-time processors using PolarFire SoC MSS Configurator software tool, which includes presets for symmetric multiprocessing, asymmetric multiprocessor, or real-time modes that optimize system performance.

As mentioned, L1 and L2 cache can be implemented as deterministic memory and branch prediction can be left on or off, a rich operating system and hard-real time components to reside in the same coherent CPU cluster.

Commercial RTOS solutions such as Amazon FreeRTOS, µC/OS, Nucleus, ThreadX, VxWorks, and Zephyr RTOSs have been ported to the Icicle board. It also supports Microchip’s PolarFire SoC Linux software development kit (SDK), which is available in Yocto and buildroot environments and integrates secure system boot, secure bootloader, crypto services, inter-CPU messaging, and drivers for both the CPU subsystem and FPGA fabric.

On the security front, the RISC-V CPU architecture leverages a five-stage, single-issue in-order execution pipeline that isn't susceptible to exploits like Spectre and Meltdown found in many out-of-order processors, and each of the RISC-V cores features physical memory protection (PMP). A physically unclonable function (PUF) located in the system controller provides secure key storage for the DPA-resistant secure boot process, and the encrypted bitstream is also protected from differential power analysis.

An anti-tamper block is present on the chip as well.

Given the amount of features, headroom, and system flexibility available on the devices, it's remarkable that PolarFire SoC FPGAs deliver exceptional performance per watt versus SRAM-based SoC FPGAs from competitors like Xilinx despite having additional FPGA and DSP resources.

Shown below are comparative CoreMark scores.

 

Getting Started with the Microchip PolarFire SoC FPGA Icicle Kit

The Icicle Kit includes the PolarFire SoC FPGA MPFS250T-FCVG484EES Icicle board; an Ethernet cable; a Micro USB cable; a 12V, 5A AC power adapter and cord; quick start card; and FlashPro programming device.

In addition to the PolarFire SoC MSS Configurator mentioned earlier, users will need the Libero SoC Design Suite in order to maximize development on the Microchip PolarFire SoC FPGA Icicle Kit. The Libero suite includes synthesis, simulation, constraint management, programming, and debug tools, while MSS Configurator generates a Libero MSS component for the FPGA and C data structures that initialize the memory map in the embedded environment. 

Users can download the Libero SoC Design Suite  for free when registering for a silver license. They will also need the SoftConsole Development Environment, an Eclipse-based IDE that supports C/C++ development and debug, and includes integrated Renode debug models for the PolarFire SoC FPGAs and Icicle Kit. It is freely available for download here.

To help newcomers get Linux up and running on the Icicle Kit, Microchip has developed a quick-start Linux demo that can be completed in a couple of minutes. After configuring the jumpers appropriately, connecting the kit to a development PC and power source, and launching a terminal app, users must set the four-lane serial UART port to the following:

1. 115200 baud
2. Eight data bits
3. No flow control
4. No parity

Afterward, entering a simple "dmesg I grep tty” command in a Linux-based terminal application (Windows instructions listed here), power cycling the board, and logging back into terminal with the username "root" will have Linux running on the Icicle.

To go a step further and launch a webserver, users simply connect the included Ethernet cable to the Icicle Kit and a router that is connected to a development PC. Then, in the MMUART0 terminal, simply change the webserver directory to “$ cd /opt/microchip/iiohttpserver”, run the “$ ./run.sh” script to launch the webserver, and run  “$ ifconfig” to find the Icicle Kit’s IP address. Finally, just navigate to that IP address from a browser on the host development platform to view the webpage being served by the Icicle Kit.

Additional builds, documentation, images, and libraries can be found on the PolarFire SoC Github. The Icicle is also part of the Mi-V Ecosystem, which provides access to compatible tools from vendors such as AdaCore, antmicro, DornerWorks, EmCraft Systems, HEX-Five Security, IAR Systems, Imperas, UltraSoC, wolfSSL, and others.

For more information on Microchip's PolarFire SoC FPGA, consult the video overview embedded below or follow the resource links at the bottom of the page.

 

• PolarFire SoC FPGA Icicle Kit Overview: https://www.microsemi.com/existing-parts/parts/152514#overview
• PolarFire SoC FPGA Device Family Overview: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga#block-diagram
• Libero SoC Development Suite: https://www.microsemi.com/product-directory/design-resources/1750-libero-soc
• PolarFire SoC MSS Configurator: https://www.microsemi.com/product-directory/soc-design-tools/5587-pfsoc-mss-configurator-tool
• SoftConsole Development Environment: https://www.microsemi.com/product-directory/design-tools/4879-softconsole
• Microchip Website: https://www.microsemi.com/