Moortec Launches In-Chip Monitoring Solution for Arm's Neoverse N1 System Development Platform

May 2, 2019 Laura Dolan

PLYMOUTH, England. Moortec released its In-Chip Monitoring solution on TSMC 7nm FinFET process for the new Arm Neoverse N1 System Development Platform (SDP), which is the first 7nm infrastructure-specific system development platform in the industry, allowing asymmetrical compute acceleration through the CCIX interconnect architecture.

Moortec and Arm joined forces on a solution that dynamically senses in-chip conditions that improve power consumption, maximize system speed, and enhance device reliability that will help both hardware and software developers execute hardware prototyping, software development, system validation, and performance profiling/tuning.

"Arm Neoverse solutions are designed to deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices," said Arm’s VP of marketing, Infrastructure Line of Business, Mohamed Awad. "Our collaboration with Moortec on the N1 SDP test chip demonstrates how another piece of validated IP fits within the Neoverse platform, accelerating development and adoption of Arm-based solutions across the infrastructure." 

"Through our collaboration, we are helping to enhance performance and efficiency of Arm's next-generation compute technology on 7nm. By contributing our high accuracy embedded sensing fabric to the development of the Neoverse N1 SDP, we're enabling customers to benefit from higher performance and reliability within machine learning, artificial intelligence and data analytics applications," said Stephen Crosher, CEO of Moortec.

To learn more, visit http://www.moortec.com.

Previous Article
Intrinsyc Launches Qualcomm Snapdragon-based Hardware Development Kit
Intrinsyc Launches Qualcomm Snapdragon-based Hardware Development Kit

The Snapdragon 855 Mobile HDK is an open-frame solution based on an Android 9 operating system that deliver...

Next Article
SiFive Partners with QuickLogic for Rapid Chip Design SoC Templates

SiFive, a provider of RISC-V core IP, recently announced its Freedom Aware (FA) family of SoC templates as ...