Lattice sensAI 3.0 Halves Power Consumption, Doubles Performance on CrossLink-NX FPGAs

May 20, 2020 Brandon Lewis

Lattice Semiconductor has released  version 3.0  of its sensAI edge inferencing  solutions stack,  which delivers several updated features and support for the company's 28 nm FD-SOI CrossLink-NX  family of low-power FPGAs. According to Lattice, CrossLink-NX devices running sensAI software double performance and consume half the power versus prior versions of the stack.

Key enhancements in sensAI version 3.0 include:

  • New CNN accelerator IP that takes advantage of parallelism,  2.5  Mb of distributed memory and block RAM, and additional DSP resources in the CrossLink-NX FPGA architecture
  • Updates to  the NN compiler tool that simplifies the  compilation and download of trained models to CrossLink-NX FPGAs.
  • Added support for MobileNet v2, SSD, and ResNet models on Lattice ECP5 FPGAs
  • A VGG-based object counting demo that yields 10 fps at only 200 mW on CrossLink-NX FPGAs.

Lattice plans to continue releasing new out-of-the-box application demos and reference designs via the sensAI platform.

For more information, visit

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at

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