Achronix Pushes FPGAs to the Max

August 30, 2019 Rich Nass

Recently, Achronix Semiconductor, a provider of FPGA-based hardware accelerator devices, introduced its Speedster7t family, aimed at the demands of artificial intelligence (AI), machine learning (ML), and other high-bandwidth networking applications that can benefit from high levels of acceleration. The company claims that the devices are based on a new, highly optimized architecture. This latest FPGA architecture balances on-chip processing, interconnects and external I/O, to maximize data throughput.

The Speedster7t family includes a two-dimensional network-on-chip (NoC), and a high-density array of machine-learning processors (MLPs). Hence, the NoC spans horizontally and vertically over the FPGA fabric, connecting to all of the FPGA’s high-speed data and memory interfaces, supporting the high-bandwidth communication needed between on-chip processing engines.

Each row or column in the NoC is implemented as two 256-bit, unidirectional industry-standard AXI channels operating at 2 GHz, delivering 512 Gbps of data traffic in each direction simultaneously. The NoC also eliminates the congestion and performance bottlenecks that occur in traditional FPGAs that use the programmable routing and logic lookup table (LUT) resources to move data streams throughout the FPGA.

The configurable MLPs consist of blocks that support integer formats from 4 to 24 bits and efficient floating-point modes including direct support for TensorFlow’s 16-bit format as well as the supercharged block floating-point format that doubles the compute engines per MLP. The MLPs are tightly coupled with embedded memory blocks, eliminating the delays associated with FPGA routing.

From a security perspective, Speedster7t FPGAs offer advanced bitstream features with multiple layers of defense. Keys are encrypted based on a tamper-resistant physically unclonable function (PUF), and bitstreams are encrypted and authenticated by 256-bit AES-GCM. To defend against side-channel attacks, bitstreams are segmented, with separately derived keys used for each segment, and the decryption hardware employs differential power analysis (DPA) counter measures. In addition, a 2048-bit RSA public key authentication protocol is used to activate the decryption and authentication hardware.

Manufactured on TSMC’s 7nm FinFET process, Speedster7t devices include high-bandwidth GDDR6 interfaces, 400-Gbit Ethernet ports, and PCI Express Gen5. They range from 363K to 2.6M 6-input LUTs. Achronix’s ACE design tools that support all of company’s products are available today. The first devices and development boards for evaluation will be available in Q4 2019.

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About the Author

Rich Nass

Richard Nass is the Executive Vice-President of OpenSystems Media. His key responsibilities include setting the direction for all aspects of OpenSystems Media’s Embedded and IoT product portfolios, including web sites, e-newsletters, print and digital magazines, and various other digital and print activities. He was instrumental in developing the company's on-line educational portal, Embedded University. Previously, Nass was the Brand Director for UBM’s award-winning Design News property. Prior to that, he led the content team for UBM Canon’s Medical Devices Group, as well all custom properties and events in the U.S., Europe, and Asia. Nass has been in the engineering OEM industry for more than 25 years. In prior stints, he led the Content Team at EE Times, handling the Embedded and Custom groups and the TechOnline DesignLine network of design engineering web sites. Nass holds a BSEE degree from the New Jersey Institute of Technology.

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