Infineon Technologies is addressing advanced power management design with the Source Down industry standard packaging concept. The first power MOSFETs launched in this new package is the OptiMOS TM 25V in a PQFN measuring 3.3x3.3 mm. The package concept connects the source potential (instead of the drain potential) to the thermal pad, increasing power density and performance.
Two different footprint versions are currently available. The Source-Down Standard-Gate footprint is based on the current PQFN 3.3x3.3 mm pinout configuration, and the location of the electrical connection remains the same. For the Center-Gate version, the gate-pin is moved to support parallel configuration of multiple MOSFETs. With its larger drain-to-source creepage distance, it is possible to connect the gates of multiple devices on a single PCB layer, as well as a wider source area for improved electrical connection.
This technology innovation results in major reduction of R DS(on) by up to 30 % compared to current technology. The thermal resistance between junction to case (R thJC) is also significantly improved compared to the current PQFN packages, as well as reduced parasitics, improved PCB losses, and superior thermal performance.
The OptiMOS Source-Down will be showcased at Infineon’s booth 1510 at the 2020 Applied Power Electronics Conference and Exposition (APEC), which takes place in New Orleans, LA from March 16-18.