TSMC 40ULP Process Helps Ambiq Micro Achieve 6 µA/MHz

July 8, 2019 Brandon Lewis

Ambiq Micro has stated that its Arm Cortex-M4F-based Apollo3 Blue Wireless SoC has achieved active power consumption of less than six microamperes per megahertz (6 uA/MHz) thanks to TSMC’s 40 nm ultra-low-power (40ULP) low-Vdd process technology. Combined with Ambiq’s Subthreshold Power Optimized Technology (SPOT), the 40ULP process will enable the Apollo3 wireless SoC in battery-powered designs.

The Apollo3 Blue Wireless SoC integrates a dedicated core for BLE5 stacks, a DMA engine, QSPI interface, microphone inputs, and advanced stepper motor control for analog management.

TSMC’s 40ULP technology provides low-leakage transistors, which help Apollo3 SoCs conserve power by optimizing leakage paths in gates and junctions. The low-Vdd solution is supported by multiple Vt option transistors, and deliver a standard cell operating voltage of 0.7V. An eHVT ultra-low-leakage transistor and ultra-low-leakage (SRAM) bitcell are also incorporated into the Apollo3 design.

The Apollo3 Blue Wireless SoC is the basis for Ambiq’s Voice-on-SPOT reference platform.

For more information, visit ambiqmicro.com.

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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