SmartDV Offers New Design IP for DDR5, LPDDR5

March 16, 2020 Perry Cohen

SmartDV Technologies introduced its new Design IP for DDR5 and LPDDR5 SDRAM controllers.

The DDR5 and LPDDR5 Design IP offers low power and latency, reduced gate count for increased memory interface bandwidth, and supports the latest DDR5 and LPDDR5 specifications. Applications such as high-performance computing, networking, wearables, IoT and mobile are targeted by the IP.

SmartDV's DDR5 Controller Design IP Core supports the JESD79-5 Rev095 protocol standard specification, while its LPDDR5 Controller Design IP core supports the JESD209-5 LPDDR5 protocol standard specification. The IPs are compatible with DFI 5.0 and support f host bust interfaces such as AHB, APB, OCP, TileLink, Wishbone, VCI, and Avalon PLB.

For more information, visit http://www.smart-dv.com/

About the Author

Perry Cohen

Perry Cohen, associate editor for Embedded Computing Design, is responsible for web content editing and creation in addition to podcast production. He also assists with the publication’s social media efforts which include strategic posting, follower engagement, and social media analysis. Before joining the ECD editorial team, Perry has been published on both local and national news platforms including KTAR.com (Phoenix), ArizonaSports.com (Phoenix), AZFamily.com, Cronkite News, and MLB/MiLB among others. Perry received a BA in Journalism from the Walter Cronkite School of Journalism and Mass Communications at Arizona State university. He can be reached by email at <a href="mailto:perry.cohen@opensysmedia.com">perry.cohen@opensysmedia.com</a>. Follow Perry’s work and ECD content on his twitter account @pcohen21.

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