New to Riviera-PRO: VHDL-2019 Support and a UVM Registers Window

June 30, 2020 Tiera Oliver

Aldec has added VHDL-2019 feature support and a UVM Registers window to Riviera-PRO, the company's simulation and debugging tool.

The VHDL-2019 features supported are: Interfaces, Conditional Compilation, Shared Variables on Entity Interfaces, API for Assert (without PSL), API for Calling Path Information (in debug mode), Conditional Expression and API to access Date, Time, and File System.

As for the UVM Registers window, it lists UVM RAL register models and their properties. Register models can be viewed as a hierarchy of register blocks or as a memory map. The contents of registers and their fields from the UVM model, plus the HDL implementation, are visualized in this window, which can be exported as CSV files for use as input data for the register generator.

The new release of Riviera-PRO also has updated UVVM libraries. Updated to the 2020 03 03b version of the open-source and Universal VHDL Verification Methodology.

Riviera-PRO 2020.04 is now available for download and evaluation.

For more information, visit:

About the Author

Tiera Oliver, edtorial intern for Embedded Computing Design, is responsible for web content edits as well as newsletter updates. She also assists in news content as far as constructing and editing stories. Before interning for ECD, Tiera had recently graduated from Northern Arizona University where she received her B.A. in journalism and political science and worked as a news reporter for the university's student led newspaper, The Lumberjack.

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