Mirabilis Design announced the VisualSim RISC-V system modeling and simulation environment. VisualSim provides a RISC-V modeling package for developers of RISC-V IP, designers of RISC-V processors and systems engineers developing applications using RISC-V components.
The package contains configurable RISC-V core, vendor-specific RISC-V processors, TileLink, DMA, peripherals, RTOS, and memory modules. The library components are compatible with the rest of the hardware, software, schedulers and network library from Mirabilis Design.
The VisualSim enables product designers to evaluate feasibility, eliminate risk and identify system bottlenecks of products using RISC-V. In the VisualSim environment, the user constructs a model of the product, adds the traffic and sensor interfaces and defines the user-cases. This model is simulated with different parameter values and scenarios. The generated reports provide visibility into timing deadlines, power consumption, resource efficiency, deadlocks, buffer occupancy, data overflow, quality of service, and functional correctness.
In the RISC-V library from Mirabilis Design, the application templates support the modeling effort and enable new modelers to put together a system. The eco-system consists of common trace interfaces, task graph generators, pre-configured reports, and a visualizer that pinpoints the system behavior. The models can be built as a combination of stochastic and timing-accuracy. According to the company, the VisualSim RISC-V system is the first RISC-V package that allows for true trade-off studies.
To introduce this RISC-V solution, Mirabilis Design is conducting a complementary RISC-V Webinar on May 27. Register at: https://www.mirabilisdesign.com/sign-up/
VisualSim RISC-V is available as a standard library option in VisualSim 2020. VisualSim Architect is available on Windows, Linux, and MAC OS.
For more information, visit: https://www.mirabilisdesign.com/
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