Mentor announced it has achieved certification for a number of its integrated circuit (IC) design tools for TSMC’s N5 and N6 process technologies. Further, the collaboration between Mentor and TSMC has been broadened to advanced packaging technology; this leverages Mentor’s Calibre platform 3DSTACK packaging technology.
The goal of TSMC’s N5 and N6 process technologies is to increase performance, reduce power consumption, and decrease form factor size.
According to the company, the Mentor IC design technologies recently certified for TSMC’s N5 and N6 processes are:
• The Calibre nmPlatform, which is the IC physical verification industry leader. Calibre delivers outstanding performance, accuracy and reliability for the world’s most successful chipmakers and IC designers.
• The Calibre xACT extraction tool - a component of the larger Calibre nmPlatform that delivers robust parasitic extraction functionality and highly accurate parasitic data for post-layout analysis and simulation.
• Mentor’s Analog FastSPICE (AFS) Platform, which provides leading-edge circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory and custom digital circuits.
Mentor also made the announcement that its AFS platform is now supporting TSMC’s mobile and high-performance computing (HPC) design platform. This allows Mentor’s customer working with analog, mixed-signal and radio frequency (RF) designs for HPC applications to verify chips in the TSMC processes.
For more information, visit http://www.mentor.com.
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