Lattice Semiconductor released a new Single Wire Aggregation (SWA) IP solution for reducing overall system size and BOM cost in industrial, consumer, and computing applications. It features the Lattice iCE40 UltraPlus FPGA.
The purpose of the new SWA is to allow developers to reduce the number of board-to-board and component-to-component connectors in embedded designs to increase reliability and reduce overall system footprint and cost.
“The solution is a strong fit for both novice and expert FPGA developers,” said market segment manager at Lattice Hussein Osman, in a press release. “Its pre-configured bitstreams help those new to FPGA-based design quickly configure an SWA application without requiring HDL coding experience, while the solution’s support for expanded parameterization makes it easy for FPGA experts to combine the Lattice SWA bitstreams with their own HDL code.”
Lattice’s SWA provides hardware and software developers required to implement a single wire interface capable of aggregating multiple common I/O (I2C, I2S, UART and GPIO) data streams between components and circuit boards in a system.
The aggregated I/O configurations that are being offered include the following:
- Two I2S, an I2C peripheral, an I2C controller, and eight GPIO signals
- Six I2C controller and two GPIO signals
- One I2C controller and 12 GPIO signals
- Three I2C controller, two I2C peripheral, and 15 GPIO signals
- One I2S, one I2C controller, one I2C peripheral, and eight GPIO signals
For more information, visit https://www.latticesemi.com/singlewire.
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