Lattice CrossLink-NX FPGA Integrates Mixel MIPI D-PHY IP

May 19, 2020 Brandon Lewis
Mixel's MIPI D-PHY IP solution has been integrated with Lattice Semiconductor's 28 nm Crosslink-NXTM FPGAs. The D-PHY v1.2 link supports between one and four lanes at 2.5 Gbps per lane for  a maximum aggregate data rate of 10 Gbps per instance.
 
The Mixel MIPI D-PHY Universal IP provides transmit and receive functionality for MIPI CSI-2 and MIPI DSI applications. Proprietary features allow the solution to reduce standby current and wake-up time.
 
Lattice was able to achieve first-time silicon success when incorporating the IP into their latest-generation devices based on the FD-SOI Lattice Nexus FPGA platform. An earlier generation of Mixel D-PHY Universal IP was integrated into the CrossLink Programmable ASSP.
 
To  date,  Mixel MIPI IP has  been silicon proven in nine  nodes from eight foundries.
 
For more information, visit https://mixel.com/
 
 
 

About the Author

Brandon Lewis

Brandon Lewis, Editor-in-Chief of Embedded Computing Design, is responsible for guiding the property's content strategy, editorial direction, and engineering community engagement, which includes IoT Design, Automotive Embedded Systems, the Power Page, Industrial AI & Machine Learning, and other publications. As an experienced technical journalist, editor, and reporter with an aptitude for identifying key technologies, products, and market trends in the embedded technology sector, he enjoys covering topics that range from development kits and tools to cyber security and technology business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached by email at brandon.lewis@opensysmedia.com.

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