Khronos Steps Towards Widespread Deployment of SYCL with Release of SYCL 2020 Provisional Specification

By Tiera Oliver

Associate Editor

Embedded Computing Design

June 30, 2020

News

Khronos Steps Towards Widespread Deployment of SYCL with Release of SYCL 2020 Provisional Specification

Features are available now in Intel's DPC++ & Codeplay's ComputeCpp; developers encouraged to provide feedback on the publicly available specification for C++ based heterogeneous parallel programming.

Khronos Group announced the ratification and public release of the SYCL 2020 Provisional Specification. SYCL is a standard C++ based heterogeneous parallel programming framework for accelerating High Performance Computing (HPC), machine learning, embedded computing, and compute-intensive desktop applications on a wide range of processor architectures, including CPUs, GPUs, FPGAs, and AI processors.

The SYCL 2020 Provisional Specification is publicly available to enable feedback from developers and implementers before the eventual specification finalization and release of the SYCL 2020 Adopters Program, which will enable implementers to be officially conformant-tentatively expected by the end of the year.

A royalty-free open standard, SYCL 2020 enables programmer productivity through a domain-specific language, compact code, and simplified common patterns, such as Class Template Argument Deduction and Deduction Guides, all while preserving backwards compatibility with previous versions. SYCL 2020 is based on C++17 and includes new programming abstractions, such as unified shared memory, reductions, group algorithms, and sub-groups to enable high-performance applications across diverse hardware architectures.

A beta implementation of SYCL 2020 is available in Intel's DPC++. Codeplay's ComputeCpp SYCL 1.2.1 conformant implementation includes selected SYCL 2020 features as extensions, with more being added over time. Both implementations are based on the Clang open-source compiler framework. Developers can download either implementation and experiment with SYCL 2020 features today.

At the Argonne National Laboratory, Exascale supercomputer systems using Intel chips are being built and new implementations seek to enable developers to scale C++ applications to accelerator clusters using SYCL. In Europe, the Cineca Supercomputing center is using the Celerity distributed runtime system, built on top of SYCL, to program the new Marconi100 cluster equipped with 3,920 GPUs and ranked #9 in the Top500 (June 2020).

SYCL 2020 continues to leverage OpenCL as a backend target to reach into diverse processor accelerator architectures, but the latest SYCL implementations are adding additional backends, providing enhanced deployment flexibility for SYCL developers.

To provide feedback on the SYCL 2020 specification, visit the Khronos SYCL Community Forum.

For more information, visit: https://www.khronos.org/registry/SYCL/

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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